Specializing in Analog CAD Automation, Machine Learning-driven circuit sizing, and RNM (Real Number Modeling) for high-speed VLSI interfaces at AMD. Passionate open-source EDA contributor and ASIC tapeout instructor.
Read my profile summary, academic honors at NITK (9.6 Honors GPA), and my core engineering philosophy across physical design and automation.
Deep dive into my contributions at AMD (Analog CAD & ML Circuit Sizing), Intel Corporation (Ansys Redhawk IR Drop), and Texas Instruments (DAC Trimming).
Explore 6+ major hardware & software projects including RISC-V OpenLane tapeout, FPGA CNN accelerators, 5-stage pipelined CPU, and AES encryption modules.
Review my technical arsenal across VLSI CAD tools (OpenLane, Magic, Ansys Redhawk, XModel), HDLs (Verilog, SystemVerilog), and Python/TCL scripting.
Review my current industry CAD automation initiatives at AMD alongside my distinguished collegiate foundations: Rank 13 in IEEE SPCup 2021 Globally and IEEE NITK CASS Chair tenure.
Read detailed technical articles and lab notes written in markdown on Analog CAD workflows, ML circuit automation, and ASIC design methodologies.