July 2023 – Present · Full-time

Silicon Design Engineer 2

AMD

  • Build system-level analog mixed-signal verification environments with XMODEL and MODELZEN across process corners.
  • Perform formal verification, static property checking, and logic equivalence checking with Synopsys ESP and Cadence Conformal LEC.
  • Develop internal Python and TCL automation for analog circuit sizing, verification flows, and regression testing.
  • Explore machine-learning-driven circuit generation from target frequency responses.
  • XMODEL
  • MODELZEN
  • Python
  • TCL
  • Conformal LEC
  • Synopsys ESP
Industry work →

August 2022 – February 2023 · Undergraduate internship

Structural Design Intern

Intel Corporation

  • Performed structural reliability verification through IR-drop checks and power-grid analysis using Ansys Redhawk.
  • Worked on design automation for chip layout and floorplanning.
  • Maintained tools for cross-tool result analysis and automated report summarization.
  • Ansys Redhawk
  • IR-drop analysis
  • TCL
  • Perl

May 2022 – July 2022 · Undergraduate internship

Analog VLSI Intern

Texas Instruments

  • Developed capacitor-trimming algorithms to calibrate a high-speed DAC for fabrication variation.
  • Built configurable Python tooling for test chips and automated control of voltage sources, oscilloscopes, and signal generators.
  • DAC calibration
  • Python
  • Lab automation