Analog CAD automation
Python and TCL tooling for circuit sizing, verification workflows, and repeatable regressions.
Related experience →Projects
Models, automation, and hardware systems—from professional verification flows to academic implementations.
Python and TCL tooling for circuit sizing, verification workflows, and repeatable regressions.
Related experience →Behavioral models with XMODEL and MODELZEN, alongside formal verification and equivalence checks.
Related experience →Exploring PicoRV32 configurations and physical-design tradeoffs through OpenLane.
Read the case study →A standard-cell ALU in Magic VLSI, checked through an automated simulation workflow.
Read the case study →Scalable FPGA memory architecture for convolution pixel reuse across changing kernel and stride sizes.
FPGA · CNN · VerilogA five-stage CPU paired with a custom Python GUI assembler.
Computer architecture · PythonA 32-bit RISC processor with a 128-bit AES block and assembler-side encryption.
RISC · AESAn embedded object-detection pipeline using MobileNet-SSD V2.
Edge AI · PythonMore code and experiments on GitHub ↗
9 repositories
AI portfolio website test
Open repo ↗Source and project history on GitHub.
Open repo ↗Source and project history on GitHub.
Open repo ↗Gemini Pro 3.1 test project
Open repo ↗This is part of EC383 - Mini Project in VLSI Design.
Open repo ↗Source and project history on GitHub.
Open repo ↗Submission for Bot the builder
Open repo ↗CS50-Webdev-Week1 Git Practice
Open repo ↗A Multiple Choice Quiz Created Using JavaScript
Open repo ↗No repositories match. Try a different search or language.