Industry

AMD

Analog CAD automation

Python and TCL tooling for circuit sizing, verification workflows, and repeatable regressions.

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AMD

Mixed-signal modeling and verification

Behavioral models with XMODEL and MODELZEN, alongside formal verification and equivalence checks.

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Academic

PicoRV32RTL configurationOpenLanePhysical implementation
Academic · NITK

RISC-V, from RTL to layout.

Exploring PicoRV32 configurations and physical-design tradeoffs through OpenLane.

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A [3:0]B [3:0]ADD · AND · OROUT
Academic · NITK

Four bits. From layout to verification.

A standard-cell ALU in Magic VLSI, checked through an automated simulation workflow.

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Configurable CNN hardware framework

Scalable FPGA memory architecture for convolution pixel reuse across changing kernel and stride sizes.

FPGA · CNN · Verilog

MIT Beta-ISA pipelined processor

A five-stage CPU paired with a custom Python GUI assembler.

Computer architecture · Python

Security module for a microprocessor

A 32-bit RISC processor with a 128-bit AES block and assembler-side encryption.

RISC · AES

Raspberry Pi object detection

An embedded object-detection pipeline using MobileNet-SSD V2.

Edge AI · Python

Public repositories

More code and experiments on GitHub ↗

9 repositories

Portfolio website

JavaScript

AI portfolio website test

Open repo ↗

Codex RISCV 64bit Processor

SystemVerilog

Source and project history on GitHub.

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Antigravity RISCV 64bit Processor

Verilog

Source and project history on GitHub.

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Antigravity jellyfin client

Kotlin

Gemini Pro 3.1 test project

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RISC V based micro controller using OpenLane

Verilog

This is part of EC383 - Mini Project in VLSI Design.

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4 Bit ALU using Magic VLSI

Python

Source and project history on GitHub.

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Hydra Bot the builder

Python

Submission for Bot the builder

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Multiple Choice Quiz JavaScript

Source codeFork

A Multiple Choice Quiz Created Using JavaScript

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