Case study
A small ALU, checked from the layout up.
Standard-cell layout in Magic VLSI with automated switch-level verification.
- When
- November 2021
- Where
- NITK · Prof. Ramesh Kini
- Work
- Academic layout and verification project
From operations to physical layout
I implemented a four-bit ALU for addition, bitwise AND, and bitwise OR using Pharosc standard cells in Magic VLSI. The project connects logic design with a physical layout and an automated check of its behavior.
Implementation and verification
Magic extracts the layout to a .sim representation, which IRSIM simulates at switch level. A Python generator produces simulator commands, and a Bash script runs the workflow.
The result checker compares AND and OR outputs with Python’s bitwise operations. Addition includes the carry-out bit when calculating the observed result. Random input vectors make repeated checks easier to run.
Verification results
The repository includes the layout, extracted simulation file, command generator, verification code, and a project report. The checks exercise randomized inputs rather than exhaustive verification.